ppt : 4 학년 2학기 adc 쪽에 있음.
Abstract
[Implementation: 2 highly interleaved analog-to-digital converters(ADCs)]
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필요성 : communication require faster converters + CMOS 공정이 더 이상 significant speed advantages X , emerging wired communication standard 는 ADCs 에 build 됨. 점점 더 same band 에서 data rate 를 올려서 higher-order modulation 을 할 것이다. 즉 ADCs with at least 8 bit resolution at high sampling rate 가 지속적으로 성장할 것이다.
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그래서 8 bit 이상 resolution 을 위해 뭐가 효율적이냐 : SAR ADCs ⇒장점: flexible architecture, power efficiency, suitability for digital CMOS process. 즉, low total number of comparisons to determine the digital output + absence of amplification during conversion(amp 는 pipelined ADCs의 특징, amp의 부재로 인해 low supply voltage 에서 converter가 동작)단점: slower clock rate.
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Time-interleaved front end sampler + SAR ADCs ⇒ High speed converter ⇒ TI- ADCs 디자인은 divide-and-conquer approach 채택(power and area 가 sub-ADC에 의해 결정됨. speed & bandwidth & interleaving accuracy 는 front end interleaver(-analog input signal demultiplexing structure 이며 sampling stage + buffter 로 구성)에 의해 결정)
- 2개의 서로 다른 ADCs architecture(for sampling the input signal onto the sub-ADCs, 우리는 voltage-based sampling at high sampling rates를 봐서 analog input BW 가 limiting factor + hold time of sampled signal 이 중요한 문제)에서 analog input bandwidth & hold time for sampled signals & constraints on the clock path 에 대한 trade-off 존재
- 둘 다 CMOS SOI technology
- Goal : voltage-based time interleaved sampling for 100Gb/s communication system
ADCs architecture 6bit 8bit input bandwidth > 20GHz > 20GHz inline demux sampling 32X interleaving 64X interleaving sampling rate 36GS/s at 110mW 90GS/s at 667mW SNDR above 31.6 dB at 36 GHz(Nyquist) above 36 dB up to 6.1 GHz, above 33 dB up to 19.9 GHz Area $0.048 mm^2$ $0.45 mm^2$
Section 2 : High-Speed, Low-Power ADCs: fundamental ADC limits & Design Tradeoffs
A. Interleaved ADCs Requirements (High-speed)
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enables the separation of ADC requriements (Interleaver 용 // sub-ADCs 용)
- Interleaver : consume less power and area, input bandwidth 와 nonlinearity 를 만족해야함
- sub-ADCs : 얘가 대부분의 power 를 쓰니까 optimize , single sub-ADCs should have max( speed/ power) & max( speed/ area), area가 작을수록 signal routing from interleaver to sub-ADCs 에 용이함.
→ 둘 다 total noise budget 에 기여(ADC 가 higher speed & precision requirement 일수록, interleaver 에 더 많은 noise budget 이 할당되어야 함-interleaver 가 technology constraint 에 의해 더 강하게 bound 됨)
→ skew and BW mismatch 는 오직 first sampling stage 에만 영향을 주고, gain mismatch and offset 은 sub-ADCs 에도 영향을 줄 수 있음(차이 확인!)
B. Noise and Distortion Budget of an ADC
(1) SNDR(signal-to-noise and distortion ratio): A(amplitude of input signal), $V_{i,pp-diff}$(maximum peak-peak differential input voltage), N(resolution of ADCs), $\sigma_{DNL}$ & $\sigma_{INL}$(standard deviation of DNL and INL in LSBs), $f_in$(input frequency), $\sigma_j$(std of timing jitter in seconds), $\sigma_n$(std of thermal noise in ADCs) ⇒effects from time interleaving 은 (1)식에 포함 X
$$ SNDR_{tot}= 10\log{\frac{\frac{1}{2}A^2}{\frac{V^2_{i,pp-diff}}{2^{2N}}(\frac{1}{12}+\frac{1}{4}{\sigma_{DNL}^2}+\sigma_{DNL}^2)+(\sqrt2\pi f_{in}A\sigma_j)^2+\sigma_n^2}} $$
- 분모 다 전개했을때 첫번째 항: Quantization noise 이며 오직 sub-ADCs 에 의해서만 영향받음
- INL, DNL, thermal nosie : Interleaver+ sub-ADCs 둘 다에 의해서 영향을 받음(Interleaver 의 nonlinearity + $\frac{kt}{C}$ noise by sampling capacitor (resistor에의한 noise는 무시))
- Timing jitter : 오직 Interleaver 에만 영향을 줌(up to the first sampling stage), clock signal to sample the ADC input signal 은 thermal noise 와 power supply noise 에 의해 timing jitter 를 보임. available power budget on the clock path 는 minimum achievable clock jitter due to thermal noise 를 결정함(jitter 2배로 줄이기 위해서 4배의 power 필요) ⇒제일 Advanced jitter 는 50-60 fs
(2) SNDR limit from jitter
$$ SNDR_{jitter}=-20\log(2\pi f_{in}\sigma_j) $$
Section 3 : Voltage-based time-interleaving architectures for high-speed ADCs (+resolution high 여도 ok )
- Analog input bandwidth of an interleaved sampler
- Hold time available to process the sample
- 결론: 어떤 interleaving architecture 가 specification을 잘 만족?
- 판단 기준 : by relating the analog input bandwidth to hold time on the sampling capacitor ⇒ sampling clock 이 필요하다 ⇒분석은 switch type에 따라 진행(NMOS or PMOS & boot-strapped switches)
A. Voltage-Based Interleaver Architectures
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direct sampling & inline demux sampling 으로 catagorize⇒ 둘 다 implement subsampling for larger interleaving ratio
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Direct Sampling:
Fig. 1. Direct sampling with buffered subsampling [2] . Waveforms are shown for 50% duty cycle clocking
- provide shortest path from input to sampling CAP with minimum resistance
- 1개 이상 sampling switch 가 동시에 closed
- 1개의 sampling switch만 close 되면 highest bandwidth but shortest sampling pulsed required
- 너무 많은 스위치 달리면 Vi 에 input capacitance 증가
- sampled voltage 는 Cs에 보관되고 forwared through a buffer and demux structure to sampling capacitor of sub-ADC $C_{s,ADC}$
- Inline demux sampling:
Fig. 2. Inline demux sampling with buffered subsampling [4] .
- stack 2 switches to reduce the number of parallel switches at the input
- 닫히는 순서: lnline demux switch ⇒ Sampling switch
- 열리는 순서 : Sampling switch ⇒ lnline demux switch
- 결국 sampling time 은 오직 sampling switch clock 의 falling edge에만 영향
- Inline demux switch : timing critical clock signal 의 수를 현저히 감소
- 결론: parallel sampling switches 감소 ⇒ smaller input capacitane + the increased resistance of 2 series-connected switches
B. Interleaver Model
- analog input bandwidth 는 sampling capacitor size에 달려있다.(target SNDR을 위한 $\frac{kT}{C}$nosie 에 의해 요구되는 정도 C size로 설계)-chap6 24p
- analog input bandwidth 는 input network에도 영향받음
- high speed ADC의 경우 input is often terminated with a 50Ω resistor to reduce signal reflections
- ADC sees a 25Ω resistance from the termination resistor and the input source resistance
- lower resistance 가 higher bandwidth 를 위해 더 좋다.(resistance noise 를chap 6에서 봤을 때 동일한 bw에 대해서 저항 값이 커질수록 noise power(bw구간 동안 적분)가 커지니까, 동일한 noise power에 대해 저항 값이 작을수록 bw가 넓을 거다) 걍 간단하게 말해서 저항이 작을수록 resistance noise도 줄어드니까 bw of interest 에 대해 적분해도 output resistance 얼마 안나온다. 그러니까 전체 noise power 가 일정하다면 적분할 수 있는 bw of interest가 넓어짐!
- low resistance 얻는 방법
- introducing a buffer with a low output impedance : buffer transistor 로 인해 inherent bandwidth limit
- using a resistive divider as termination resistor : signal swing at the ADC
- input resistance + capacitor size + interleaver architecture(앞에 2개 결정되면 우리가 자유롭게 할 수 있는거는 interleaver architecture: the number of switches in each stage and sizing)
- Direct & demux sampling interleaver 공부 전에 simplified switch model부터 적용
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Fig. 3. Simplified switch model
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total gate capacitance (= drain cap + source cap + bulk cap)
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on-resistance of the switch
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drain cap 과 source cap은 constant(independant of gate voltage)라 가정하고, leakage from sampling cap in switch-off state 는 없다 가정
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transition frequency 는 gate cap과 on-resistance of the switch 로 표현 가능
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effective transition frequency = p* transition frequency
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p = correction factor = $\frac{ due\ to\ wiring\ of\ a\ sampling\ switch}{due\ to\ without\ wiring\ of\ a\ sampling\ switch} of\ parasitic\ capacitance\ + R_{on}$ = or by simulating the transfer function of inter leaver and fitting p
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(동일한 기술로 만든 difference interleaver는 p 거의 동일)
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C. Inline Demux Sampling Model
- fig4는 fig5로 simplify됨
Fig. 5.
RC equivalent of the inline demux interleaver from Fig. 4.
Section 4 : Implementation and measurement results of high-speed CMOS ADC at 90 GS/s & 8 bit resolution(667 mW power consumption) + low-power implementation at 36 GS/s & 6 bit resolution(100 mW power consumption)